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Time-triggered architecture
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Time-triggered architecture : ウィキペディア英語版
Time-triggered architecture
Time-triggered architecture (abbreviated as TTA), also known as a time-triggered system, is a computer system that executes one or more sets of tasks according to a pre-determined task schedule.〔Pont, M.J. (2001) "Patterns for Time-Triggered Embedded Systems", Addison-Wesley / ACM Press. ISBN 0-201-331381.〕 Implementation of a TT system will typically involve use of a single interrupt that is linked to the periodic overflow of a timer. This interrupt may drive a task scheduler (a restricted form of real-time operating system). The scheduler willin turnrelease the system tasks at predetermined points in time.〔
== History and development ==

Because they have highly deterministic timing behaviour, TT systems have been used for many years to develop safety-critical aerospace and related systems.〔Ward, N. J. (1991) "The static analysis of a safety-critical avionics control system", in Corbyn, D.E. and Bray, N. P. (Eds.) "Air Transport Safety: Proceedings of the Safety and Reliability Society Spring Conference, 1991" Published by SaRS, Ltd.〕
Use of TT systems was popularised by the publication of ''Patterns for Time-Triggered Embedded Systems'' (PTTES) in 2001〔 and the related introductory book ''Embedded C'' in 2002.〔Pont, M.J. (2002) "Embedded C", Addison-Wesley. ISBN 0-201-79523-X.〕 The PTTES book also introduced the concepts of time-triggered hybrid schedulers (an architecture for time-triggered systems that require task pre-emption) and shared-clock schedulers (an architecture for distributed time-triggered systems involving multiple, synchronised, nodes).〔
Since publication of PTTES, extensive research work on TT systems has been carried out.〔Athaide, K.F., Pont, M.J. and Ayavoo, D. (2008) "Deploying a time-triggered shared-clock architecture in a multiprocessor system-on-chip design", in Proceedings of the 4th UK Embedded Forum (September 2008, Southampton, UK).〕〔Ayavoo, D., Pont, M.J., Short, M. and Parker, S. (2007) "Two novel shared-clock scheduling algorithms for use with CAN-based distributed systems", Microprocessors and Microsystems, 31(5): 326–334.〕〔Chan, K.L. and Pont, M.J. (2010) "Real-time non-invasive detection of timing-constraint violations in time-triggered embedded systems", Proceedings of the 7th IEEE International Conference on Embedded Software and Systems, Bradford, UK, 2010, pp.1978–1986. Published by IEEE Computer Society. ISBN 978-0-7695-4108-2.〕〔Gendy, A.K. and Pont, M.J. (2008) "Automatically configuring time-triggered schedulers for use with resource-constrained, single-processor embedded systems", IEEE Transactions on Industrial Informatics, 4(1): 37–46.〕〔Hughes, Z.M. and Pont, M.J. (2008) "Reducing the impact of task overruns in resource-constrained embedded systems in which a time-triggered software architecture is employed", Transactions of the Institute of Measurement and Control, Vol. 30: pp.427–450.〕〔Phatrapornnant, T. and Pont, M.J. (2006) "Reducing jitter in embedded systems employing a time-triggered software architecture and dynamic voltage scaling", IEEE Transactions on Computers, 55(2): 113–124.〕

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